Side wall contact in a nonvolatile electrically alterable memory cell
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United States of America Patent
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Jun 11, 1991
Grant Date -
N/A
app pub date -
Aug 3, 1988
filing date -
Aug 3, 1988
priority date (Note) -
Expired
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Abstract
A nonvolatile integrated circuit memory cell (10) is provided which is smaller in size than conventional memory cells and uses only two layers of polysilicon with floating gate portion (50) of the memory cell formed partly from a first polysilicon layer (20) and partly from second polysilicon layer (26), contact between the two portions being made using residual polysilicon bridge or overlapping portion (34) between the two layers. The invention enables programming and erase tunneling oxides to be formed in a single step while maximizing the capacitive coupling between the floating gate (50) and the substrate (12) by forming a silicon dioxide layer (102) between the floating gate and substrate separately from formation of the programming (30) and erase (28) tunneling elements.
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