Variable latency method and apparatus for floating-point coprocessor
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United States of America Patent
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Jun 4, 1991
Grant Date -
N/A
app pub date -
Jan 19, 1990
filing date -
Jan 19, 1990
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A programmable latency (a programmable number of clock cycles) needed for an operation completion. The required latency for a pipe is determined from a formula including the system clock cycle time which the unit will be specified to operate under. The latency is preprogrammed by setting the count of a timer accordingly to provide at least the minimum number of clock cycles necessary to cover the time required to do the computation. Separate timers are independently set for arithmetic logic unit (ALU) operations, multiply operations, logical operations and divide and square root operations.
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