Bus receiver power-up synchronization and error detection circuit
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United States of America Patent
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Apr 30, 1991
Grant Date -
N/A
app pub date -
Dec 19, 1988
filing date -
Dec 19, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A bus receiver power-up synchronization circuit synchronizes the receipt of parallel data messages transferred asynchronously as three byte words preceded and succeeded by idle bytes so as to receive complete and not partial messages. Also, the receiver scrutinizes the messages for faults and for too many or too few bytes.
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