System for testing internal nodes
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United States of America Patent
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Apr 30, 1991
Grant Date -
N/A
app pub date -
May 17, 1988
filing date -
May 17, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The testing circuit for testing internal nodes of a device includes storage for storing the test addresses of selected internal nodes in the device. A decoder responds to a test command from a microprocessor for selecting the test addresses from the storage and supplies the test addresses to an address bus in place of other addresses supplied to the address bus. A test decoder responds only to the test addresses on the address bus for enabling the transfer of data between the selected internal nodes in the data bus for testing the selected internal nodes.
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