Dynamic random access memory with improved sensing and refreshing
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United States of America Patent
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Feb 5, 1991
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N/A
app pub date -
Jul 20, 1989
filing date -
Jul 20, 1989
priority date (Note) -
Expired
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Abstract
The present invention uses two pairs of cross coupled n-channel sense amplifier transistors attached between two electrically balanced halves of a bit line. Disposed between each pair of cross coupled n-channel sense amplifier transistors is only one pair of p-channel restore transistors attached between the bit line and complement bit line. Furthermore, on the bit line and complement bit line, between one pair of cross coupled n-channel sense amplifier transistors and the pair of p-channel restore transistors, are depletion type isolating transistors that further isolate halves of the bit line and complement bit line.
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