Importance

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Abstract

An apparatus (50) activates and drives sense amplifiers in a dynamic random access memory (DRAM) at a high speed. The sense amplifier includes a P-MOS sense amplifier (15, 16) and an n-MOS sense amplifier (18, 19). The P-MOS sense amplifier is connected to a power line (31) through a first switching element (22) to be activated while the n-MOS sense amplifier is connected to a ground line (30) through a second switching element (20) to be activated. The sense amplifier driving apparatus includes a capacitor (34) conneced between the power line and the ground line. This enables compensation for the charge and discharge currents which flow in the bit line charging and discharging operations, reduction in the bit line charging and discharging times, and suppression of the fluctuation in supply potential, improving the operating speed of the DRAM. This capacitor (34) has an electrode and a dielectric which are made of the same materials with those of a memory cell capacitor (6) comprised in a memory cell, and the dielectric is formed to be of the same film thickness also as that of the memory cell capacitor. The memory cell has a stack-type structure, where the capacitor comprises at least two capacitance elements connected in series.

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First Claim