Technique for providing a sign/magnitude subtraction operation in a floating point computation unit
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United States of America Patent
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Dec 18, 1990
Grant Date -
N/A
app pub date -
Sep 28, 1988
filing date -
Sep 28, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system for use in a floating point computation unit for providing a sign/magniture subtraction operation, which system uses propagate/generate logic responsive to the subtraction operands to produce intermediate and final propagate and generate outputs. First carry computation logic is responsive to the final propagate and generate outputs and to a carry-in bit to produce final carry outputs and a carry-out bit. The latter outputs are used to produce a first subtraction result. Second carry computation logic responds to the intermediate propagate and generate outputs to produce second final carry outputs. The latter outputs and selected intermediate propagate outputs are used to produce a second subtraction result. The carry-out bit then selects one of the two subtraction results as the final subtraction result.
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