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Abstract

A parallel analog-to-digital ('A/D') converter utilizing only N comparators and at least N-1 summing networks made of the simple resistance elements. The A/D conversion process operates asynchronously without need for registers, a clock circuit or latches and determines at a high rate of speed the N output bits for a given analog input signal. Each of the summing networks produces a composite analog signal which is fed into a respective one of the comparators. The digital output bit produced by each comparator is fed into the summing networks associated with those comparators whose output bits are less significant. Accordingly, when all output bits are changing on account of a new analog input value, the converter determines the most significant bit first, the next most significant bit next, and so on, until the least significant bit is determined. Because only simple resistive elements need be used in the summing circuit, the performance of the converter is determined principally by the switching speed of the comparators. The summing networks receive voltage inputs and produce an analog voltage output in accordance with weights which vary from one another by a predetermined power of two, as is established by the relative conductance of the resistance elements.

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