TTL/CMOS level translator
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United States of America Patent
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Oct 16, 1990
Grant Date -
N/A
app pub date -
Sep 12, 1989
filing date -
Sep 12, 1989
priority date (Note) -
Expired
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Abstract
The present invention implements a static inverter-type TTL/CMOS level translator. The present invention utilizes a pair of transistors to suppress hot electron effects. The transistor pair limits maximum VDS to VCC-VTN at the first and second gain stages. A pair of resistors serve as a virtual VCC modulator to minimize voltage variations, stabilizing the VIL/VIH trip point. The resistors also minimize standby current so that the translator of the present invention can be used in a low standby current environment. The translator of the present invention provides faster speed, wider process margins, better reliability and lower standby current than prior art translators.
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