Reduced latchup in precharging I/O lines to sense amp signal levels
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United States of America Patent
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Oct 9, 1990
Grant Date -
N/A
app pub date -
Jul 22, 1988
filing date -
Jul 22, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
I/O lines on a CMOS circuit are precharged to preferred voltage levels in order to avoid latch up. The precharging is achieved by using N channel transistors to provide a precharge which is at a threshold voltage (V.sub.T) below bias voltage V.sub.CC, or (V.sub.CC -V.sub.T). This results in a lower forward bias when V.sub.CC bumps down after the I/O lines are floated. By lowering the precharge voltage by a level corresponding to a threshold voltage (V.sub.T), the allowed range of power supply voltage bumping is increased by this amount. This eliminmates the destructive effect of a negative bump of V.sub.BE, which would have presented a diode forward bias condition. Instead, the power supply may bump to (V.sub.BE +V.sub.T).
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