Semiconductor memory device with dual selection circuitry including CMOS and bipolar transistors
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 2, 1990
Issued Date -
N/A
app pub date -
Oct 31, 1989
filing date -
Mar 16, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor memory device is provided which includes a plurality of memory arrays each including main word lines, sub word lines to which a plurality of memory cells are connected, and a decoder which selectively connects the sub word lines to the main word lines. The main word lines are relatively short, since they are isolated electrically between memory arrays, and their resistance can thus be relatively low. The main word lines are not directly connected with a plurality of memory cells, and this results in a smaller capacitance coupled to the main word lines than is customarily the case. Consequently, the semiconductor memory device can have an enhanced operating speed.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully