Clock skew avoidance technique for pipeline processors
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United States of America Patent
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Aug 14, 1990
Issued Date -
N/A
app pub date -
Aug 3, 1989
filing date -
Apr 10, 1987
priority date (Note) -
Expired
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Abstract
A technique for providing skew compensation particularly in association with a pipelined processor. The skew occurs between first and second clock signals. The skew compensation technique of the invention provides for the proper transfer of information between stages even though the clock signals may have a skew greater than the inter-stage delay. A holding or latching means is provided between stages so as to hold the previous stage data for clocking into the subsequent stage register.
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