Integrated N-channel power MOS bridge circuit
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United States of America Patent
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-
Aug 14, 1990
Grant Date -
N/A
app pub date -
Sep 6, 1985
filing date -
Dec 18, 1984
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The disclosed bridge circuit is fabricated using power MOS technology. Common terminals of the bridge circuit are integrated into common regions in the implementation. Electrodes, typically coupled together in the bridge circuit, are implemented by a shared conducting region in the integrated circuit of the semiconductor chip. By integrating the elements of the circuit, less area of the semiconductor chip is required as compared to an implementation involving 4 (four) discrete elements. Diodes are fabricated across the transistors to protect the elements against reverse biasing.
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