Addressing of redundant columns and rows of an integrated circuit memory
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United States of America Patent
Stats
-
Aug 7, 1990
Grant Date -
N/A
app pub date -
Mar 2, 1988
filing date -
Mar 3, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for the addressing of redundant elements of an integrated circuit memory is disclosed. This memory comprises an array of row memory elements and column memory elements, respectively addressable by row addresses and column addresses, at least one battery of fuses to store the address of a faulty element of the memory. The method consists: for one battery, in associating said battery with a row/column address pair; in memorizing, through the blowing of certain fuses in the battery after the testing of a memory element, the address either of a column element if the faulty element is a column element or that of a row element if the faulty element is a row element; and in enabling only the row addresses when the stored address is that of a row element or only the column addresses when the stored address is that of a column element, to address either a row redundant element or a column redundant element.
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