Dummy/trim DAC for capacitor digital-to-analog converter
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 7, 1990
Grant Date -
N/A
app pub date -
Oct 24, 1989
filing date -
Oct 24, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
In one embodiment, a successive approximation analog-to-digital converter having a main CDAC and a trim CDAC includes resistors in the main CDAC connected in series with various bit switch FETs. The resistors are precisely matched to equivalent resistances of trimmable voltage divider circuits connected in series with various corresponding bit switch FETs in the trim DAC, to prevent non-linear parasitic capactiance and voltage-current properties of first and second clamping FETs from 'unbalancing' the voltages on the charge summing conductors of the main DAC and the trim DAC during turn-off of the first and second clamping FETs after they have been turned on to equalize the voltages of the charge summing conductors. In another embodiment, separate trim and dummy DACs are provided to improve the accuracy to which the resistances in the main CDAC and trim CDAC can, as a practical matter, be matched.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully