Bias voltage generator and method
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United States of America Patent
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Jul 31, 1990
Grant Date -
N/A
app pub date -
Nov 10, 1988
filing date -
Nov 10, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A circuit for producing a reference voltage includes an NPN transistor having its emitter connected to a first terminal, its collector connected to a second terminal, a PNP transistor having its emitter connected to the second terminal, its base connected to the base of the NPN transistor, and having its collector connected to the second terminal. A current source is connected to either the first terminal or the second terminal to force a current which is divided into a current through the PNP transistor and another current through the NPN transistor. The circuit produces a reference voltage equal to the sum of the PNP V.sub.BE voltage and the NPN V.sub.BE voltage. The reference voltage tracks precisely with variations in saturation currents of the PNP transistor and the NPN transistor. The circuit is useful in producing a two V.sub.BE bias voltage between the base of an NPN pullup transistor and a PNP pulldown transistor having a common emitter connection to an output terminal. The circuit produces a constant quiescent bias current in the NPN pullup transistor and the PNP pulldown transistor that is substantially independent of variations in the saturation currents of the PNP transistor and the NPN transistor.
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