Memory error correction system
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United States of America Patent
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Apr 24, 1990
Grant Date -
N/A
app pub date -
Jun 20, 1988
filing date -
Jun 20, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system for correcting soft memory failures such as alpha particle failures in a dynamic random access memory and in a computer system wherein writeback caches are employed in a system bus environment. The address field and source identification code associated with a detected data error are stored. A generic bus request signal is generated and upon a bus grant a read message is issued on the system bus having an address field and destination address code corresponding to the stored address field and source identification code. In response to the read message, the device indicated by the identification code writes back to memory the correct data corresponding to the address field.
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