Conductance-modulated integrated transistor structure

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 4920399
SERIAL NO

07418962

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, an ohmic contact to the source regions, and a Schottky contact to each of the drain regions. The dopant concentration of the drain regions is sufficiently low to prevent the Schottky contact from forming an ohmic contact with the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two Schottky contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the Schottky diodes. Minority and majority carriers injected by the Schottky diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
LINEAR INTEGRATED SYSTEMS INCFREMONT CA

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hall, John H San Jose, CA 51 749

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation