High-performance programmable logic device
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United States of America Patent
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Apr 17, 1990
Grant Date -
N/A
app pub date -
Aug 26, 1987
filing date -
Aug 26, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A programmable logic device having greater design flexibility through use of a plurality of programmable macrocells in conjunction with programmable gate arrays. Each macrocell includes a programmable reconfigurable register for receiving sum terms from the array, and an input/output (I/O) terminal connected to receive an output from the programmable reconfigurable register. Two separate feedbacks from the macrocell to the gate array are provided. The first feedback has multiple inputs including the register output, and the second feedback has multiple inputs including the I/O terminal. Accordingly, the I/O terminal and the register can function independently. Each sum term is capable of serving multiple functions as determined by the programming of the macrocell whereby the input terms can be utilized to implement two completely independent sum-of- product logic functions, both combinatorial and one combinatorial and one sequential, and whereby each is capable of being programmably routed as feedback to the array or as an output to the I/O terminal.
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