Flexible VLSI on-chip maintenance and test system with unit I/O cell design
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United States of America Patent
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Mar 27, 1990
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N/A
app pub date -
Oct 23, 1987
filing date -
Oct 23, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.
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