Method and apparatus for qualifying branch cache entries
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United States of America Patent
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Jan 16, 1990
Grant Date -
N/A
app pub date -
Jul 31, 1987
filing date -
Jul 31, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A look ahead fetch system for a pipelined digital computer is provided for predicting in advance of decoding the outcome of a branch instruction. The system includes a branch cache having a plurality of associative sets for storing branch target addresses indexed by the lowest significant bits of the corresponding branch instruction's address. A memory for storing a coupling bit vector indicative for each branch cache set of whether the set contains a corresponding branch target address. The coupling bit vector is used to guide prediction logic to the correct branch cache sets for qualifying the entry there contained having an index corresponding to a fetched instruction's address for formulating a prediction of the next instruction to be processed.
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