Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices

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United States of America Patent

PATENT NO 4892836
SERIAL NO

07028842

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Abstract

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This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.

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Patent Owner(s)

Patent OwnerAddress
SGS MICROELETTRONICA S P A95121 CATANIA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Andreini, Antonio Milan, IT 9 139
Contiero, Claudio Buccinasco, IT 22 608
Galbiati, Paola Monza, IT 19 450

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