An integrated controlled FET switch
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United States of America Patent
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Dec 26, 1989
Grant Date -
N/A
app pub date -
May 27, 1988
filing date -
May 27, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A switch means designed as an integrated circuit possesses two series-connected FETs (Q1P, Q2P; Q1N, Q2N) whose common switching point (N5, N6) is clamped via a clamp FET (Q3N, Q3P) to a reference potential. The conductivity type of the clamp FET (Q3N, Q3P) is opposite the conductivity type of the two series-connected FETs (Q1P, Q2P; Q1N, Q2N). In the case of an n-channel clamp FET (Q3N), the latter is connected to negative potential. In the case of a p-channel clamp FET (Q3P), it is connected to positive potential.
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