Improved logic cell array using CMOS E.sup.2 PROM cells
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United States of America Patent
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Dec 5, 1989
Grant Date -
N/A
app pub date -
Aug 19, 1987
filing date -
Aug 19, 1987
priority date (Note) -
Expired
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Abstract
A programmable memory cell useful in a logic cell array draws no D.C. power in either a '1' or a '0' state. The cell includes a CMOS transistor pair including a p-channel transistor connected to a positive voltage source and an n-channel transistor connected to a circuit ground potential. The cell output is connected to a common terminal of the CMOS transistor pair. The CMOS transistor pair has a common floating gate which is selectively charged for programming the cell. In a preferred embodiment, the floating gate comprises a first polycrystalline silicon layer (polysilicon), and capacitive means including a second polysilicon layer spaced from and capacitively coupled with the first polysilicon layer is utilized to selectively applying charge to the common floating gate.
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