Phase-offset signal generator
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United States of America Patent
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Dec 5, 1989
Grant Date -
N/A
app pub date -
Dec 16, 1988
filing date -
Dec 16, 1988
priority date (Note) -
Expired
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Abstract
A device for generating a digitizing pulse for sampling an analog video signal includes a phaes-locked-loop (PLL) circuit and a phase offset circuit. The PLL circuit generates a correction pulse required to bring an output signal of digitizing pulses in phase with a reference horizontal sync signal. The phase offset circuit includes a digital memory which stores a digital number representative of a fraction of a pixel pulse that is desired as phase offset of the digitizing pulse. This fraction is converted into an offset current pulse having a duration equal to the duration of a pixel pulse and an amplitude that is the fraction of a maximum amplitude. The offset current is added to the PLL correction current for generating an output signal of digitizing pulses having the desired phase offset relative to the pixel pulses.
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