Low power dual-mode CMOS bias voltage generator
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United States of America Patent
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Nov 28, 1989
Grant Date -
N/A
app pub date -
Dec 2, 1987
filing date -
Dec 2, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A substrate voltage bias generator is disclosed including a charge pump whose output is clamped during charge pump capacitor charging cycles to zero volts thereby eliminating a voltage drop associated with prior art clamping diodes. The charge pump further includes a stand-by and booted mode, the stand-by mode providing a first level of output current at a specified generated substrate bias voltage and in the booted mode generating increased output current and voltage. The increased voltage is generated across the charge pump capacitor by a second capacitor that is only operative in the booted mode and whose charge is shared with the charge pump capacitor thereby developing a higher voltage across the charge pump capacitor. The output voltage generated by the substrate bias generator is detected and if it is too low a voltage, the booted mode is turned off. An external signal determines whether the stand-by mode or booted mode are selected.
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