Instruction sequencer for network structure microprocessor
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United States of America Patent
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Oct 31, 1989
Grant Date -
N/A
app pub date -
Apr 30, 1987
filing date -
Sep 13, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The invention concerns an instructions sequencer for microprocessor wherein the sequencer presents an architecture, a circuit conception and a presents that improves the compacity and facilitates conception and adaptation operations to different instructions sets, the sequencer having a line and column architecture and very widely produced in the form of a transistor and capacitor matrix, functioning with decoding transistors, preload transistors and a matrix for defining the phases of operating cycles.
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