Cascade FET logic circuits
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United States of America Patent
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Oct 31, 1989
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N/A
app pub date -
Oct 13, 1988
filing date -
Mar 13, 1987
priority date (Note) -
Expired
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Abstract
A group III-V digital logic circuit which includes either at least two enhancement type metal semiconductor field effect transistors and one load element or two first type field effect transistors having a first threshold voltage and two second type field effect transistors having a second threshold voltage, for providing a logic operation. The second threshold voltage is less than zero and is less than the first threshold voltage. The group III-V digital logic circuit can be formed as an integrated circuit on, in particular, a GaAs substrate. The field effect transistor can be either a metal semiconductor field effect transistor or a junction field effect transistor.
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