Importance

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Abstract

A unique data recovery circuit which is able to recover transmitted digital data with a data clock embedded therein. No initial timing signals are required for operation of the data recovery circuit. Instead the data clock is recovered from the received data and used to synchronize the flow of data through the circuit. Noise pulses and other anomalous transients are rejected by the circuit so that the data output accurately corresponds to the data transmitted. Operation of the invention is achieved through a number of expedients which include a random access memory delay line which delays interpretation of the data until the data clock has been recovered. A uniquely integrated delay switching network is utilized to switch recovery of the clock from the received data to the delayed data. A phase locked loop and an integrate, sample and dump circuit are also employed, both of which use asynchronous ripple counters to achieve the primary objective of the invention which is to recover the data transmitted.

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First Claim