TTL compatible CMOS logic circuit for driving heavy capacitive loads at high speed
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United States of America Patent
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-
Sep 19, 1989
Grant Date -
N/A
app pub date -
Dec 9, 1987
filing date -
Dec 10, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
CMOS logic circuit with one or more inputs has at least a complementary pair of transistors, the N-channel driver transistor having a gate directly connected to an input while the P-channel load transistor having a gate connected to the output of the second one of two inverters connected in cascade, the input of the first inverter being connected to the input of the circuit. Using two signal inverting stages or inverters for mirroring the input signal on the gate of the load P-channel transistor of the circuit pair permits the defining of the triggering threshold of the circuit with great freedom, the obtaining of a greater switching speed and the reduction of power dissipation under stand-by conditions. The invention is particularly suited for HCT circuits.
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