Single chip successive approximation analog-to-digital converter with trimmable and controllable digital-to-analog converter
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United States of America Patent
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Jul 25, 1989
Grant Date -
N/A
app pub date -
Dec 18, 1987
filing date -
Dec 18, 1987
priority date (Note) -
Expired
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Abstract
A single chip monolithic integrated successive approximation analog-to-digital converter includes a test mode terminal for receiving shift register test mode control signals and successive approximation mode control signals. Digital test data signals are applied to a test data terminal. A trimmable digital-to-analog converter (DAC) is connected to receive digital signals and converts these signals to analog signals of corresponding values. A successive approximation and shift register is coupled to the test mode terminal and the test data terminal. During post-fabrication processing, the successive approximation and shift register operates in a shift register test mode in response to the test mode control signals. Test signals of a known value are serially received and applied in parallel to the DAC. The DAC can then be trimmed to required specifications. The successive approximation and shift register operates in a successive approximation mode in response to successive approximation mode control signals.
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