Importance

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Abstract

A digital signal processor includes a global RAM that is accessable by an external high priority bus, a microprocessor and an I/O controller. The global RAM is accessed by a global address bus and a global data bus. The global address bus is coupled by separately selectable buffers to a microprocessor address bus, the external address bus, and an I/O bus, respectively. The global data bus is coupled by separately selectable transceivers to the microprocessor data bus, the external bus, and the I/O bus, respectively. Either the microprocessor or the I/O port controller may request and be granted access to the global memory at any time if it is not already being accessed. If the external bus requests access to the global RAM and either the microprocessor or the I/O port controller is accessing the global RAM, multiple wait states are inserted into that microprocessor or I/O port controller until the external bus completes its access. The microprocessor or I/O controller then automatically continues accessing the global RAM.

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First Claim