Processor for signal processing and hierarchical multiprocessing structure including at least one such processor
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United States of America Patent
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Jul 4, 1989
Issued Date -
N/A
app pub date -
Feb 19, 1988
filing date -
Aug 14, 1984
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A processor formed from a signal processing unit operating according to instructions transmitted by a bus line, including a slave section provided with an address/data port for connection to a master signal processing circuit; a first buffer register in which data coming from the master processing circuit via the address/data port can be written and read in order to be processed by the processing unit, a second buffer register in which the data processed by the processing unit can be written, then read in order to be directed via the address/data port to the master processing circuit and a sequential control circuit so that access to these buffer registers is allocated in turn to the processing unit and to the master processing circuit. A master section is also provided intended to be connected to at least one slave circuit.
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