Bit-serial integrator circuitry
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United States of America Patent
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Jun 20, 1989
Grant Date -
N/A
app pub date -
Aug 24, 1987
filing date -
Aug 24, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A bit-serial integrator includes the cascade combination of a bit-serial adder, a first bit-serial register and a second bit-serial register. Input signal is applied to one input of the adder and the output terminal of the second bit-serial register is coupled to a second input of the adder. A transparent latch is coupled to an output of the first bit-serial register and is conditioned to pass a predetermined number of sample bits and then to latch and output a particular sample bit for the duration of a sample period. The output of the latch is an integrated, scaled and truncated representation of the input signal.
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