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Abstract

A telemetry data processor for processing extremely high bandwidth data such as that associated with telemetry from spacecraft. A demultiplexer (1) distributes the data onto several channels (CHl through CHn), each comprising a (preferably split-cycle synchronous) processing bus (BUSl through BUSn). Processing can occur on each of the n buses simultaneously. Several processor modules (P boards) are directly coupled to each processing bus, with each P board directly coupled to two buses. Several memory modules (M boards) are directly coupled to each processing bus, with each M board directly coupled to two buses. The functions and architectures of the P boards and M boards are described, along with those of D boards (disk controller modules) and I boards (modules for interfacing the telemetry data processor with its outside environment, which may comprise local area networks, peripherals, gateways, etc.).

First Claim