Antilock brake system
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United States of America Patent
Stats
-
Jun 6, 1989
Issued Date -
N/A
app pub date -
Jul 7, 1988
filing date -
Jan 31, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A antilock brake system utilizes a microprocessor controller to monitor the rate of speed decay of a braked wheel of a vehicle and to cause release of braking force under incipient wheel lock-up conditions. The microprocessor receives a single digital wheel speed input signal and processes the latter in accordance with a program whereby a reference signal is generated and is periodically compared with the wheel speed signal to determine if a lock-up condition is in progress. The microprocessor compares the speed signal with the reference signal at frequent sampling intervals and when the wheel speed decreases at a rate exceeding a desired value, the reference signal is varied by the microprocessor to decrease at a predetermined first rate of decrement until the wheel speed signal and the reference signal correspond to each other, indicating that the wheel speed is dropping at a rate in excess of a desired rate of speed decay. The microprocessor adjusts the rate of decrement of the reference signal at a second maximum rate and generates a brake release signal to relieve the brake force applied to the wheel. When the wheel speed signal again crosses over the reference signal, the brake force is restored and the reference signal again tracks the wheel speed signal at a value less than the wheel speed signal. The microprocessor determines whether the weel is on a high or low friction surface and compensates for the latter by extending the brake release signal to provide additional time for the wheel to regain velocity. The microprocessor controller restricts the maximum time of brake release signal generation during each brake release cycle. The wheel speed sensing system and microprocessor controller are located remote from the braked wheel and in close proximity to each other to minimize the effects of shock, vibration and electrical interference. A failsafe circuit arrangement is also disclosed as part of the microprocessor controller.
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