Input offset voltage trimming network and method
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United States of America Patent
Stats
-
May 2, 1989
Grant Date -
N/A
app pub date -
Dec 11, 1987
filing date -
Dec 11, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Trimming of input offset voltage of a diferential amplifier is provided by a pair of resistance networks which are connected to the emitters of a pair of current mirror transistors. By adjusting the resistances of the resistance networks, the adjustment currents flowing through the current mirror transistors are selected to cancel out the input offset voltage of the differential amplifier. Each resistance network includes a plurality of resistors connected in series with a low resistance shorting link connected in parallel with each of the plurality of resistances. The input offset voltage is trimmed by selectively cutting the shorting links with a two-phase measure and trim process.
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