NMOS data storage cell for clocked shift register applications
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United States of America Patent
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Apr 25, 1989
Grant Date -
N/A
app pub date -
May 13, 1985
filing date -
May 13, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An improved NMOS storage cell for use in shift registers is disclosed. Among other components, it contains a pair of inverters--one them an enabling inverter. A pre-charge transistor is placed in parallel with the first inverter to decrease the rise time associated with the transition from a logic low level output to a logic high level output. The result of adding the pre-charge transistor to the circuit is to increase the speed of operation of the storage cell, without the accompanying decrease in density with prior art methods, where the components must be enlarged. Another aspect of the present invention which further increases the density of the cell is the elimination of the complement clock line found in many prior art storage cells. The previous combination of a second inverter and a pass transistor connected to a complement clock line, is replaced by an enabling inverter connected to the clock line.
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