Structured design method for high density standard cell and macrocell layout of VLSI chips
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United States of America Patent
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Mar 21, 1989
Grant Date -
N/A
app pub date -
Jun 19, 1987
filing date -
Jun 19, 1987
priority date (Note) -
Expired
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Abstract
A chip layout system lays out chips including adjustable-shaped domains of standard cells and fixed-size macrocells. The system orders those standard cells which have interconnections into binary pairs or groupings of two. The binary pairs are grouped in higher and higher order groupings based upon evaluations of the area of the grouping and the sum of the lengths of the interconnections. All possible permutations of placement configuration including some rotations of various elements are further evaluated and the final placement is established on the basis of a minimum area, minimum interconnect length criterion. During the processing, the aspect ratios of the various domains and grouping of domains are adjusted to optimize their placement on the chip surface.
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