Clock multiplier/jitter attenuator
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United States of America Patent
Stats
-
Feb 14, 1989
Grant Date -
N/A
app pub date -
May 19, 1987
filing date -
May 19, 1987
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.
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Cited Art Landscape
Patent Citation Ranking
- 47 Citation Count
- H04L Class
- 0 % this patent is cited more than
- 36 Age