Improved semiconductor device having a polycrystalline isolation region
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United States of America Patent
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Jan 24, 1989
Grant Date -
N/A
app pub date -
Jun 24, 1982
filing date -
Jun 25, 1981
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In an improved metal-oxide-semiconductor (MOS) device a polycrystalline semiconductor region is buried in a monocrystalline semiconductor substrate at the isolation region between elements of the device. A deep and narrow groove of about 1 .mu.m is formed by reactive ion etching in which the polycrystalline silicon is deposited by chemical vapor deposition. Surface polycrystalline semiconductor is removed by etching resulting in only the polycrystalline semiconductor buried in the substrate which is implanted with ions. Alternatively, polycrystalline semiconductor is deposited only in the bottom portion of the groove, ion implanted and an insulator film is formed in the remaining portion of the groove for fully isolating the polycrystalline region. Semiconductor devices prepared in accordance with the invention have flattened surfaces, reduced crystal defects and permit further miniaturization of the MOS devices.

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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
KABUSHIKI KAISHA SUWA SEIKOSHA A COMPANY OF JAPAN | 4-1 NISHI-SHINJUKU 2-CHOME SHINJUKU-KU TOKYO 160 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Kato, Juri | Suwa, JP | 49 | 713 |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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