Improved semiconductor device having a polycrystalline isolation region

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United States of America Patent

PATENT NO 4800417
SERIAL NO

06391790

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Abstract

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In an improved metal-oxide-semiconductor (MOS) device a polycrystalline semiconductor region is buried in a monocrystalline semiconductor substrate at the isolation region between elements of the device. A deep and narrow groove of about 1 .mu.m is formed by reactive ion etching in which the polycrystalline silicon is deposited by chemical vapor deposition. Surface polycrystalline semiconductor is removed by etching resulting in only the polycrystalline semiconductor buried in the substrate which is implanted with ions. Alternatively, polycrystalline semiconductor is deposited only in the bottom portion of the groove, ion implanted and an insulator film is formed in the remaining portion of the groove for fully isolating the polycrystalline region. Semiconductor devices prepared in accordance with the invention have flattened surfaces, reduced crystal defects and permit further miniaturization of the MOS devices.

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Patent Owner(s)

Patent OwnerAddress
KABUSHIKI KAISHA SUWA SEIKOSHA A COMPANY OF JAPAN4-1 NISHI-SHINJUKU 2-CHOME SHINJUKU-KU TOKYO 160

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kato, Juri Suwa, JP 49 713

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