Protective circuit for memory devices
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United States of America Patent
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-
Jan 17, 1989
Issued Date -
N/A
app pub date -
Mar 27, 1986
filing date -
Feb 7, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A circuit for protecting the contents of memory devices, each having a power supply voltage input terminal and a disabling signal input terminal following a failure in an A.C.-derived D.C. potential in which respective time delay circuits couple battery potential to said power supply voltage terminals and to said disabling signal input terminals at respective predetermined times after said failure.
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