Cellular floating-point serial pipelined multiplier
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United States of America Patent
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Jan 17, 1989
Grant Date -
N/A
app pub date -
Jun 16, 1986
filing date -
Oct 16, 1984
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A cellular floating-point serial pipelined multiplier arranged to accept two synchronous digit serial data streams in floating-point format and to output one identically formatted stream is the floating-point product of the synchronous input members. The multiplier includes a delay circuit (1) for the X operand and a digit re-ordering/delay circuit (2) for the Y operand connected to a pipelined addition circuit (3) which outputs the product through a delay cell (6). A MODE control signal propagation and generation circuit (4) is also connected to the pipelined addition circuit (3) and to the digit re-ordering/delay circuit (2), and a cell differentiation circuit (5) is connected to control the pipelined addition circuit (3) and the digit re-ordering/delay circuit (2) and the X operand delay circuit (1).
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