Flip-flop with identical propagation delay in clock pass through mode and in normal operation
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 10, 1989
Grant Date -
N/A
app pub date -
Dec 5, 1986
filing date -
Dec 5, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A flip-flop circuit is provided for use in a phase-locked loop circuit, the flip-flop having two signal paths for selecting a VCO output during velocity lock and phase lock. The two signal paths comprise identical environments and therefore eliminate the phase step exhibited by prior art designs in shifting between velocity lock and phase lock. The circuit is also useful in any application where a clock to output delay of a flip-flop connected for normal operation, must have its propagation delay matched to a circuit which simply delays a signal by the same amount.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully