Dynamically reconfigurable array logic
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 13, 1988
Grant Date -
N/A
app pub date -
Jul 18, 1986
filing date -
Jul 18, 1986
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A dynamically reconfigurable array logic (DRAL) is capable of in-system logical reconfiguration in real time and comprises a RAM programmable logic array of bits, each bit comprising a fuse connection between logic elements. I/O means are coupled to the RAM programmable logic array for logical selection of registered output. A first register is coupled for receiving data and high-level commands. A sequencer includes a pair of up/down counters and functions to generate addresses. A timing device controls DMA transfers and issues READ and WRITE strobes. A second register monitors outputs and functions as a comparator, in a first mode, and functions to load outputs during specified time intervals in a second mode.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully