Data input circuit with digital phase locked loop
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United States of America Patent
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Oct 25, 1988
Grant Date -
N/A
app pub date -
Jul 18, 1986
filing date -
Jul 18, 1986
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A digital phase locked loop circuit for reading input data transmitted from storage media. Counter and adder components establish the time of arrival of input data bits. Inspection windows are established having durations and start/stop times that can be adjusted by correction signals so that subsequent data bits will be received in the middle of the inspection windows. Correction signals to the counter and adder components compensate for variations in the phase and frequency of input data transmitted from storage media.
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