CMOS programmable logic array using NOR gates for clocking
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United States of America Patent
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Aug 16, 1988
Grant Date -
N/A
app pub date -
Oct 15, 1985
filing date -
Oct 15, 1985
priority date (Note) -
Expired
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Abstract
A programmable logic array 100 which uses parallel transistor logic gates 150 arranged in a compact layout for fast signal propagation. One of logic planes 120 or 130 is prechargeable to substantially reduce power consumption using a simple, one-phase clock.
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