Microprocessor having multiplication circuitry implementing a modified Booth algorithm
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United States of America Patent
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Jul 5, 1988
Issued Date -
N/A
app pub date -
Apr 29, 1987
filing date -
Oct 30, 1984
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A modified Booth algorithm is implemented in the arithmetic logic of the ALU data path to cut the number of cycles to do a multiply in half thereby improving execution time of the multiplication operation. A Booth Encoder examines the two least significant bits of the multiplier stored in the Q2 register and the bit which was previously shifted out on the last partial product shift cycle. Based upon the status of these three bits, the Booth Encoder causes the ALU to add or substract one times the multiplicand to the contents of the partial product register and shift twice, add or substract two times the multiplicand to the contents of the partial product register and shift twice, or do nothing but shift twice. A pre ALU B shifter provides a single left shift of the multiplicand to provide the multiplication by two when same is necessary.
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