Noise suppression interface circuit for non-superimposed two-phase timing signal generator
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United States of America Patent
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Jun 21, 1988
Grant Date -
N/A
app pub date -
Mar 29, 1985
filing date -
Mar 30, 1984
priority date (Note) -
Expired
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Abstract
A noise suppression interface circuit, using field effect transistors of MOS type, for non-superimposed two-phase timing signal generators is described. The upper level and the lower level of the output timing signals are determined by the potentials of two circuit nodes (V.sub.H, V.sub.L) which are respectively coupled, by a first transistor (M1) and a second transistor (M2), operating at saturation, to a first supply terminal (+V.sub.DD) and a second supply terminal (-V.sub.SS) having potentials which are respectively equal and opposite to a common potential. The circuit nodes (V.sub.H, V.sub.L) are both coupled to the common potential by identical number of transistors (M3, M4; M5, M6) each coupled in a diode configuration.
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