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Abstract

A threshold receiver circuit consists of a reference subcircuit and one or more signal input subcircuits. The reference subcircuit derives a mirror voltage by regulating a reference current flowing through an external reference resistor. The mirror voltage is distributed to each of the signal input subcircuits. Within each signal input subcircuit a signal transistor has its gate connected to the mirror voltage and its drain connected to a common input node, thereby causing a signal current to flow into the common input node which is proportional to the reference current. The signal current also flows through an external signal input resistor which is connected to the input node, and into the external input signal source. The input node voltage is thus equal to the input signal source voltage plus the voltage-drop across the signal input resistor. This input node voltage is compared to an internal reference voltage by a comparator which is also connected to the common input node. Thus, a logic output signal is produced by the comparator corresponding to the magnitude of the input signal source. Hysteresis is added at the comparator reference input, and also by means of one or more hysteresis transistors whose drains are connected to the common input node. The gates of the hysteresis transistors are controlled so that when the output logic state is low, they are connected to the mirror voltage and a hysteresis current is produced, and when the output logic state is high, no hysteresis current is produced.

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